Coherent transactions limit the bandwidth for transactions from a peripheral input-output (I/O) bus in processor-based systems such as desktop computers, laptop computers and servers. Processor-based systems typically have a host bus that couples a processor and main memory to ports for I/O devices. The I/O devices, such as Ethernet cards, couple to the host bus through an I/O controller or bridge via a bus such as a peripheral component interconnect (PCI) bus. The I/O bus has ordering rules that govern the order of handling of transactions so an I/O device may count on the ordering when issuing transactions. When the I/O devices may count on the ordering of transactions, I/O devices may issue transactions that would otherwise cause unpredictable results. For example, after an I/O device issues a read transaction for a memory line and subsequently issues a write transaction for the memory line, the I/O device expects the read completion to return the data prior to the new data being written. However, the host bus may be an unordered domain that does not guaranty that transactions are carried out in the order received from the PCI bus. In these situations, the I/O controller governs the order of transactions.
The I/O controller places the transactions in an ordering queue in the order received to govern the order of inbound transactions from an I/O bus, and waits to transmit the inbound transaction across the unordered interface until the ordering rules corresponding to each transaction are satisfied in the ordering queue. When a partial write is received and only a full memory line may be written to memory, such as main memory, the data for the partial write is merged with the full memory line upon satisfying the ordering rules and then forwarded to main memory. However, buffer space must be maintained for the data of each partial write and the memory line to merge with the data for each partial write until the inbound transaction satisfies ordering requirements.
I/O devices continue to demand increasing bandwidth and unnecessary delay for transactions in an ordering queue is particularly wasteful. Further, when multiple I/O devices transmit coherent transactions to the I/O controller, transactions unnecessarily wait in the ordering queue for coherent transactions with unrelated ordering requirements and the buffer space requirements increase. A conventional way to meet increasing demand for bandwidth is to increase the number of ports available for I/O devices at the I/O controller and memory controller for main system memory. The increase in ports, however, increases complexity and cost of such a memory controller and drives up overall system cost.